SystemVerilog foreach syntax for looping through lower …
https://stackoverflow.com/questions/23136421/systemverilog-foreach-syntax-for-looping-through-lower-dimension-of-multidimensi
WebApr 17, 2014 · system-verilog. asked Apr 17, 2014 at 14:48. Victor L. 10.1k 25 88 136. 2 Answers. Sorted by: 9. You can do this: $display("Loop through i=2"); begin. automatic int i = 2; foreach (my_req[,j]) begin // notice the "," before j. $display("i:%0d,j:%0d", i, j); end. Working code on EDA Playground: http://www.edaplayground.com/x/2Qn.
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